Computing and electronic devices continue to shrink in size, even as higher performance and storage capacity is expected from the devices. Additionally, the more components and the greater the real estate used, the more the devices consume power. Size and power consumption are significant factors in electronic devices, especially handheld and mobile devices. Recent developments in electronic device manufacturing make three-dimensional (3D) circuits possible, which can significantly increase densities. Such circuits with increased densities are of particular interest for memory device applications, because of the opportunities for increased densities and power savings.
However, while 3D memory circuits are supposed to provide power savings, they can experience unexpected power inefficiencies due to their architectures. For example, in 3D memories, the wordline capacitance (CWL) increases significantly over comparable 2D structures. The 3D architecture can have wordlines in tiers and sub-blocks, which increases the effective length of the wordline, and therefore its capacitance. The increase in capacitance makes tR (read time) slower, and makes reads costlier in terms of energy per bit compare to 2D memories. In a 2D memory array consecutive read, the memory charges one wordline, reads the wordline, and then discharges the wordline. The memory then repeats the process with the next wordline. In traditional approaches to 3D memory arrays, a similar process of charging the wordline, reading the wordline, and then discharging the wordline is much more costly due to the amount of energy required to charge the wordline.
Descriptions of certain details and implementations follow, including a description of the figures, which may depict some or all of the embodiments described below, as well as discussing other potential embodiments or implementations of the inventive concepts presented herein.